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IP1818 16-port  10/100M+2-port Gigabit Smart Switch Controller

General Description :

  The IP1818 is a non-blocking, store-and-forward architecture switch controller, which supports 16-port SS-SMII, 1 Port RGMII/Serdes combo , 1 port RGMII, and one-port MII for a 16+2G smart switch application. With built-in SERDES transceiver, the IP1818 provides a very cost-effective solution for a 16+2 Gigabit fiber without external Gigabit Ethernet transceivers.  

  The IP1818 embeds a 2.75Mb SSRAM for the use of packet buffer and 4K MAC address table. It provides a 2-wire CPU interface, which allows the user to access to the register. The system configuration can be downloaded from EEPROM upon reset. The information of the serial LED showed is provided through a 2-wire interface. With the external logic devices, the IP1818 can show the status of link, speed, duplex and activity. 

  In addition to the fundamental function such as the flow control, the broadcast storm control and the programmable MAC address aging time, the IP1818 also supports many advanced features which allow the user to implement the smart switch features. The IGMP (Internet Group Management Protocol) snooping provides a method to build a multicast link without complicated CPU code. The user can also use the 2 levels of priority queue to support the real-time streaming application. Supporting both port_based and tag_based VLAN, the IP1818 can partition the network traffic by programming the VLAN table. Furthermore the IP1818 supports both non-VID related tag based VLAN and VID related tag based VLAN. The access control based on the MAC layer, the IP layer and TCP/UDP layer provides a method for the user to implement the Class of Service and the network security.  

 An MCU based web controller to work with IP1818 can easily support the web management. Users can remotely configure and monitor IP1818 smart switches through browsers, such as Microsoft Internet Explorer or Chrome and no program installation is required for the smart switch management.

Feature :

  • Provides 16 port SS-SMII, 2 RGMII, one 1000Base-X SERDES and one MII 

  • Built-in 2.75Mb RAM

  • Support packet length up to 1536 Bytes

  • Store & forward, share memory, non-blocking architecture

  • Supports flow control

    - 802.3x in full duplex

    - Collision/carrier_sense based backpressure in half duplex

  • Provides up to 4K MAC address entries

    -  CRC/ direct hashing algorithm

    -  Programmable aging timer (55s~15.7hr) error < 4 %

    -  Configurable MAC address table

    -  Optional MAC address learning

  • Supports porting mirroring function (Tx, Rx, Tx&Rx)

  • Supports IGMP snooping function

    - Version 1 and Version 2

  • Supports flexible 3 trunking groups

    - (Port 0 ~ port 3, port 4~ port 7, Gigabit port 1 ~ port 2)

    - Load balance based on (physical port, Destination MAC Address, Source MAC Address, Destination MAC Address/Source MAC Address)

  • Link failure recovery

  • Supports VLAN

    - Port based VLAN

    - Tag based VLAN

    - Add/ remove/ modify tag based on VID or physical port

  • Support Class of Service

    - Port based CoS

    -  802.1Q priority tag based

    -  IP TOS/DSCP based (IPv4/IPv6)

    -  TCP/UDP port based

    -  2 level of priority per port

    -  WRR/ First-Come-First-serve/ Strict priority

  • Broadcast storm control support

    - Broadcast rate control per port

    - Block broadcast packet that does not belong to ARP or IP packet forwarded to CPU port

  • Supports port security

    - MAC address based

    - IP address based

    - TCP/UDP port based

  • Supports Bandwidth control with/without flow control

    - 480 configurable levels for p0~p15 and MII port (from 32kbps to 63.75 Mbps)

    - 508 configurable levels for RGMII port (from 32kbps to 510 Mbps)

  • Supports 5 items port state for Spanning Tree protocol

    - Blocking/ listening/ learning/ forwarding/ disabled

    - Forward BPDU to CPU port

  • Captures the specific packet and forward it to CPU port


    - Packets with specific TCP/UDP port number

  • PHY address setting for CPU, Giga 1 and Giga2 port

  • Operating mode configuration

    - Pin initial setting

    - 2 wire serial interface for EEPROM

    - 2 wire serial interface for register setting

  •    Status counters for each port

    - RX/TX packet count

    - CRC error packet count

    - Dropped packet count

    - Collision count

  • Programmable serial driving LED functions

  • Only one 25MHz crystal is needed

  • Optional 25Mhz, 50Mhz clock output

  • Adjustable IO voltage (3.3/2.5v MII, 3.3/1.9v SS-SMII, 2.7V~1.9V RGMII)

  • 128 pin PQFP. Lead-free package


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